1. Field of the Invention
The present invention relates to a PWM control apparatus for an interphase reactor multiplex inverter in which output terminals of two inverters are connected with each other through interphase reactors so as to provide parallel multiplex three-phase output from the midpoints of the interphase reactors, and more particularly, to a control technique of the circulating current which flows through each interphase reactor to circulate between two inverters.
2. Description of the Prior Art
FIG. 1 shows a main circuit of an interphase reactor multiplex GTO PWM inverter described, for example, in a paper, No. 59-B28, entitled "Parallel Operation of GTO PWM Inverters", Transactions of Japan Society of Electric Engineers, Vol. 104, Part B No. 4, April 1984. In the figure, reference numeral 1 denotes a D.C. voltage source, 2a-7a and 2b-7b denote circulation diodes each pair thereof connected in series being connected in parallel with the D.C. voltage source 1, and 8a-13a and 8b-13b denote GTOs (gate turn-off thyristors) connected in parallel with the circulation diodes 2a-7a and 2b-7b to constitute a first inverter INV. a and a second inverter INV. b. Reference numerals 14-16 denote interphase reactors connecting output terminals of the inverters INV. a and INV. b with each other, and 17 denotes a load obtaining a parallel multiplex three-phase output from the midpoints of the interphase reactors 14-16.
FIG. 2 shows a control circuit for the main circuit of FIG. 1, wherein 18a, 18b denote oscillators, 19a, 19b denote frequency dividers, 20a, 20b denote triangular carrier generators, 22a, 22b denote local processors for generating a three-phase reference wave for pulse width modulation (PWM) of each inverter, 21 denotes a supervisory processor for controlling the local pocessors 22a, 22b, 23a-25a and 23b-25b denote comparators comparing the triangular carrier with the reference wave for generating a PWM firing signal for each of the GTOs 8a-13a and 8b-13b, 26a-28a and 26b-28b denote waveform shaping circuits suppressing the generation of narrow pulses, and 29 denotes a feedback signal for phase and amplitude of the circulating currents i.sub.uc, i.sub.vc, and i.sub.wc passing straight through the interphase reactors in FIG. 1.
Now, operations in the aforementioned circuit will be described. Since the first inverter INV. a and the second inverter INV. b in FIG. 1 are identical to each other, the operations only for the first inverter INV. a will be described.
First, the clock as the output of the oscillator 18a is counted by a U/D (up/down) counter (not shown) within the triangular carrier generator 20a, whereby a triangular wave signal e.sub.c as shown in FIG. 8 is generated to be supplied to the comparators 23a-25a.
Meanwhile, the output of the oscillator 18a is divided for its frequency by the frequency divider 19a and input to the local processor 22a as a signal for the phase of the fundamental wave of the output phase voltage. In the local processor 22a, a sine wave table stored in a ROM is read out with the aforesaid signal for the phase of the fundamental wave used as the address, whereby a three-phase sine wave signal e.sub.a is generated to be output therefrom.
The comparators 23a-25a compare, as shown in FIG. 3, the triangular wave signal e.sub.c with the sine wave signal e.sub.a thereby to generate PWM firing signals S.sub.a.
The PWM firing signals S.sub.a are passed through the waveform shaping circuits 26a-28a, whereby narrow pulses not connected with pulse width modulation are eliminated therefrom, and turned to firing signals U.sub.a, V.sub.a, and W.sub.a for the GTOs 8a, 10a, and 12a. Although firing signals for the GTOs 9a, 11a, and 13a are U.sub.a, V.sub.a, and W.sub.a which are negative logic signals of U.sub.a, V.sub.a and W.sub.a, they are not shown for the sake of simplification.
In the prior art example of FIG. 2, with the aim to achieve a redundant system for enhancement of reliability on the circuit, an individual control system is adopted, that is, the first and second inverters INV. a, INV. b are respectively operated by their individual oscillators 18a, 18b and control circuits.
Since the first and second inverters INV. a, INV. b are individually controlled as aforesaid, amplitudes and phases of the fundamental waves of the voltages generated in each phase of both the inverters become different from each other, and as a result, circulating currents i.sub.uc, i.sub.vc, and i.sub.wc as shown in FIG. 1 are caused to flow through each interphase path.
Amplitude and phase of the circulating current through each phase is fed back to the supervisory processor 21 as a feedback signal 29, and, responding thereto, the supervisory processor 21 outputs control commands to both the local processors 22a, 22b for the INV. a, INV. b such that amplitude and phase of the voltage command value (reference wave) for each phase are controlled to decrease the circulating current in each phase.
By virtue of the above described control operations, the loads shared by the inverters INV. a, INV. b can be well balanced.
Since the prior art PWM control circuit for interphase reactor multiplex inverter has been structured as described above, there have been such problems that larger interphase reactors are required for keeping the balance between the currents shared by each phase of the inverters, having different oscillation frequencies, multiplexed in the aim to obtain larger capacity, but the same cannot be used for high-speed controlling of the output currents, and further, the configuration of the control circuit becomes complex.